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verilog_cordic_core
- A highly configurable 1st quadrant CORDIC core in verilog-Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other projec
sinwave-genertor
- sinwavw generator code in verilog this will helpful for generating a sinave without using a cordic
cordic_final_program
- Verilog Code for CORDIC Algorithm
Digital-signal-process-of-PFGA
- 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
sin_cos_module
- Verilog实现的cordic算法的计算sin，cos值得模块，使用rom，代码简洁有效。-Verilog implementation of the cordic algorithm of computing the sine and cosine worth module, use of ROM, the code is concise and effective.
verilog_cordic
- 采用verilog编写的经典的cordic算法，旋转模式，亲测可用，经过了9次旋转-Classic verilog prepared by the cordic algorithm, rotation mode, pro-test available, after nine rotation
VERILOG1
- 基于FPGA的cordic算法的verilog初步实现,可以学习学习，其中也有程序解释。-FPGA based on the CORDIC algorithm Verilog initial implementation, you can learn to learn, which also has a program to explain.